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eda简易数字钟设计篇一

1、设计一个能显示1/10秒、秒、分、时的12小时数字钟。

2、时钟源使用频率为0.1hz的连续脉冲。

3、设置两个按钮，一个供“开始”及“停止”用，一个供系统“复位”用。

4、时钟显示使用数码管显示。

基于vhdl的多功能数字钟的设计 eda课程设计 资料类别课程(专业)eda 适用年级大学文件格式word+dls 文件大小1725k 上传时间2008-10-10 20:57:00 预览文件无（只能预览文件中的部分内容）下载次数0内容简介：eda课程设计 基于vhdl的多功能数字钟的设计，共11页，6086字，附源程序。摘要：介绍了利用vhdl硬件描述语言设计的多功能数字钟的思路和技巧。在max+plusii开发环境中编译和仿真了所设计的程序，并在可编程逻辑器件上下栽验证。仿真和验证结果表明，该设计方法切实可行。

eda-时钟设计-基于altera数字钟的实

现:eda课程设计 基于vhdl的多功能数字钟的设计:eda数字钟设计报告:资料包括： 论文(12页2036字)图纸说明：中文摘要：数字钟学习的目的是掌握各类计数器及它们相连的设计方法；掌握多个数码管显示的原理与方法；掌握fpga技术的层次化设计方法；掌握用vhdl语言的设计思想以及整个数字系统的设计。此数字钟设计具有时，分，秒计数显示功能，以24小时为计数循环；能实现清零，调节小时，分钟以及整点报时的功能。

eda简易数字钟设计篇二

数字钟

一、实验目的

1、掌握多位计数器相连的设计方法。

2、掌握十进制，六进制，二十四进制计数器的设计方法。

3、掌握扬声器的驱动及报时的设计。

4、led灯的花样显示。

5、掌握cpld技术的层次化设计方法。

二、实验器材

1、主芯片altera epf10k10lc84-4。2、8个led灯。

3、扬声器。4、4位数码显示管。5、8个按键开关（清零，调小时，调分钟）。

三、实验内容

根据电路特点，运用层次设计概念设计。将此设计任务分成若干模块，规定每一模块的功能和各模块之间的接口。

1、时计时程序： library ieee;use ;use ;

entity hour is

port(reset,clk : in std_logic;

daout : out std_logic_vector(7 downto 0));end hour;

architecture behav of hour is

signal count : std_logic_vector(3 downto 0);signal counter : std_logic_vector(3 downto 0);begin

p1: process(reset,clk)

begin

if reset='0' then

count<=“0000”;

counter<=“0000”;

elsif(clk'event and clk='1')then

if(counter<2)then

if(count=9)then

count<=“0000”;

counter<=counter + 1;

else

count<=count+1;

end if;

else

if(count=3)

then

counter<=“0000”;

else

count<=count+1;

count<=“0000”;

end if;

end if;

end if;

end process;

daout(7 downto 4)<=counter;daout(3 downto 0)<=count;

end behav;

2、分计时程序： library ieee;

use ;use ;

entity minute is

port(reset,clk,sethour: in std_logic;

daout : out std_logic_vector(7 downto 0);

enhour : out std_logic);end minute;

architecture behav of minute is

signal count : std_logic_vector(3 downto 0);signal counter : std_logic_vector(3 downto 0);signal carry_out1 : std_logic;signal carry_out2 : std_logic;begin

p1: process(reset,clk)begin

if reset='0' then

count<=“0000”;

counter<=“0000”;

elsif(clk'event and clk='1')then

if(counter<5)then

if(count=9)then

count<=“0000”;

counter<=counter + 1;

else

count<=count+1;

end if;

carry_out1<='0';

else

if(count=9)then

count<=“0000”;

counter<=“0000”;

carry_out1<='1';

else

count<=count+1;

carry_out1<='0';

end if;

end if;end if;end process;

p2: process(clk)begin

if(clk'event and clk='0')then

if(counter=0)then

if(count=0)then

carry_out2<='0';

end if;

else

carry_out2<='1';

end if;end if;end process;

daout(7 downto 4)<=counter;daout(3 downto 0)<=count;enhour<=(carry_out1 and carry_out2)or sethour;end behav;

3、秒计时程序： library ieee;

use ;use ;

entity second is

port(reset,clk,setmin : in std_logic;

daout : out std_logic_vector(7 downto 0);

enmin : out std_logic);end second;

architecture behav of second is

signal count : std_logic_vector(3 downto 0);signal counter : std_logic_vector(3 downto 0);signal carry_out1 : std_logic;signal carry_out2 : std_logic;begin

p1: process(reset,clk)begin

if reset='0' then

count<=“0000”;

counter<=“0000”;

elsif(clk'event and clk='1')then

if(counter<5)

then

if

(count=9)

then

count<=“0000”;

counter<=counter + 1;

else

count<=count+1;

end if;

carry_out1<='0';

else

if(count=9)

then

count<=“0000”;

counter<=“0000”;

carry_out1<='1';

else

count<=count+1;

carry_out1<='0';

end if;

end if;end if;end process;daout(7 downto

4)<=counter;

daout(3

downto

0)<=count;enmin<=carry_out1 or setmin;end behav;6

4、alert程序： library ieee;

use ;use ;

entity alert is port（clkspk : in std_logic;

second : in std_logic_vector(7 downto 0);

minute : in std_logic_vector(7 downto 0);

speak : out std_logic;

lamp : out std_logic_vector(8 downto 0));end alert;

architecture behav of alert is signal divclkspk2 : std_logic;begin p1: process(clkspk)begin

if(clkspk'event and clkspk='1')then

divclkspk2<=not divclkspk2;

end if;end process;p2: process(second,minute)begin if(minute=“01011001”)then case second is

when “01010001”=>lamp<=“000000001”;speak<=divclkspk2;when “01010010”=>lamp<=“000000010”;speak<='0';when “01010011”=>lamp<=“000000100”;speak<=divclkspk2;when “01010100”=>lamp<=“000001000”;speak<='0';when “01010101”=>lamp<=“000010000”;speak<=divclkspk2;when “01010110”=>lamp<=“000100000”;speak<='0';when “01010111”=>lamp<=“001000000”;speak<=divclkspk2;when “01011000”=>lamp<=“010000000”;speak<='0';when “01011001”=>lamp<=“100000000”;speak<=clkspk;when others=>lamp<=“000000000”;end case;end if;end process;end behav;8

5、seltime程序 library ieee;

use ;use ;

entity seltime is port（ckdsp : in std_logic;

reset : in std_logic;

second : in std_logic_vector(7 downto 0);

minute : in std_logic_vector(7 downto 0);

hour : in std_logic_vector(7 downto 0);

daout : out std_logic_vector(3 downto 0);

sel : out std_logic_vector(2 downto 0));end seltime;

architecture behav of seltime is signal sec : std_logic_vector(2 downto 0);begin

process(reset,ckdsp)begin

if(reset='0')then sec<=“000”;

elsif(ckdsp'event and ckdsp='1')then

sec<=“000”;else

sec<=sec+1;end if;end if;end process;

process(sec,second,minute,hour)begin case sec is

when “000”=>daout<=second(3 downto 0);when “001”=>daout<=second(7 downto 4);when “011”=>daout<=minute(3 downto 0);when “100”=>daout<=minute(7 downto 4);when “110”=>daout<=hour(3 downto 0);when “111”=>daout<=hour(7 downto 4);when others=>daout<=“1111”;end case;end process;

if(sec=“111”)then

sel<=sec;end behav;

6、deled程序： library ieee;

use ;use ;

entity deled is port（s: in std_logic_vector(3 downto 0);

a,b,c,d,e,f,g,h: out std_logic);end deled;

architecture behav of deled is

signal data:std_logic_vector(3 downto 0);signal dout:std_logic_vector(7 downto 0);begin data<=s;process(data)begin

case data is

when “0000”=>dout<=“00111111”;when “0001”=>dout<=“00000110”;when “0010”=>dout<=“01011011”;when “0011”=>dout<=“01001111”;when “0100”=>dout<=“01100110”;when “0101”=>dout<=“01101101”;when “0110”=>dout<=“01111101”;when “0111”=>dout<=“00000111”;when “1000”=>dout<=“01111111”;when “1001”=>dout<=“01101111”;when “1010”=>dout<=“01110111”;when “1011”=>dout<=“01111100”;when “1100”=>dout<=“00111001”;when “1101”=>dout<=“01011110”;when “1110”=>dout<=“01111001”;when “1111”=>dout<=“01000000”;when others=>dout<=“00000000”;end case;end process;h<=dout(7);

g<=dout(6);

f<=dout(5);

e<=dout(4);d<=dout(3);c<=dout(2);b<=dout(1);a<=dout(0);end behav;

7、顶层原理图：

四、实验结果 顶层原理图仿真波形：

五、心得体会

1、系统设计进要行充分的方案论证，不可盲目就动手去做；

2、实验中对每一个细节部分都要全面思考，要对特殊情况进行处理；

3、对于数字系统，要考虑同步、异步问题；

4、数字电路的理论分析要结合时序图；

5、遇到问题，要顺藤摸瓜，分析清楚，不可胡乱改动，每做一次改变都要有充分的理由；

6、模块化设计方法的优点在于其简洁性，但是在实验设计中也发现，在实验最终电路确定之前，要尽量减少模块重叠嵌套，因为在总的电路敲定之前，电路还不成熟，很多地方需要改进，如果在开始时就进行多层模块化，里层模块电路的修改将影响其外层的全部电路，这样就是牵一发动全身，很显然，这样将导致电 数字钟课程设计 电路设计的低效，所以在设计过程中，一定要尽量减少超过两层的模块；

7、遇到问题花了很长时间没有解决掉，要学会想他人请教，别人的不经意一点，可能就能把自己带出思维死区。

eda简易数字钟设计篇三

library ieee;use ;use ;use ;entity clock is port(en

:in std_logic;数码管使能

clk

:in std_logic;时钟信号

rst

:in std_logic;复位信号

sec_1

:out std_logic_vector(3 downto 0);秒高位

sec_01 :out std_logic_vector(3 downto 0);秒低位

min_1

:out std_logic_vector(3 downto 0);分高位

min_01 :out std_logic_vector(3 downto 0);分低位

hou_1

:out std_logic_vector(3 downto 0);时高位

hou_01 :out std_logic_vector(3 downto 0);时低位

bee

:out std_logic);end clock;

architecture behovior of clock is signal sec_high:std_logic_vector(3 downto 0);

signal sec_low

:std_logic_vector(3 downto 0);signal min_high:std_logic_vector(3 downto 0);

signal min_low:std_logic_vector(3 downto 0);signal hou_high:std_logic_vector(3 downto 0);

signal hou_low

:std_logic_vector(3 downto 0);

signal cy_min

:std_logic;分进位

signal cy_hou

:std_logic;时进位

signal logo_1

:std_logic;标志

signal logo_2

:std_logic;

signal logo_3

:std_logic;

begin miaolow:process(clk,rst,en)

begin

if(rst = '0')

then

sec_low <= “1000”;附给秒低位为8

elsif(clk'event and clk = '1' and en = '1')then 检测时钟上升沿及数码管使能端

if(sec_low = “1001”)then

sec_low <= “0000”;

else

sec_low <= sec_low + “0001”;加一

end if;

end if;

end process miaolow;

logo_1 <= sec_low(3)and sec_low(0);

sec_01<= sec_low;秒个位放8

miaohigh:process(clk,rst)

begin

if(rst = '0')

then

sec_high <= “0101”;

elsif(clk'event and clk = '1')then检测时钟上升沿

if(logo_1 = '1')then

if(sec_high = “0101”)then

sec_high <= “0000”;

cy_min <= '1';

else

sec_high <= sec_high + “0001”;加一

cy_min <= '0';

end if;

end if;

end if;

end process miaohigh;

sec_1 <= sec_high;秒十位放5

fenlow:process(cy_min,rst,en)

begin

if(rst = '0')

then 若复位位为0

min_low <= “1000”;则分个位为8

elsif(cy_min'event and cy_min = '1' and en = '1')then检测时钟上升沿及数码管使能端

if(min_low = “1001”)then

min_low <= “0000”;

else

min_low <= min_low + “0001”;加一

end if;

end if;

end process fenlow;

logo_2 <= min_low(3)and min_low(0);

min_01 <= min_low;分个位放8

fenhigh:process(cy_min,rst)

begin

if(rst = '0')

then

min_high <= “0101”;

elsif(cy_min'event and cy_min = '1')then检测分进位上升沿

if(logo_2 = '1')then

if(min_high = “0101”)then若分十位为5

min_high <= “0000”;

cy_hou <= '1';时进位为1

else

min_high <= min_high + “0001”;加一

cy_hou <= '0';

end if;

end if;

end if;

end process fenhigh;

min_1 <= min_high;分十位放5

shilow:process(cy_hou,rst,en)

begin

if(rst = '0')

then

hou_low <= “1001”;

elsif(cy_hou'event and cy_hou = '1'

and en = '1')then检测时进位上升沿及数码管使能端

if(hou_low = “1001”)then若时低位为9

hou_low <= “0000”;

elsif(hou_high = “0010” and hou_low = “0011”)then若时十位为2，个位为3

hou_low <= “0000”;

else

hou_low <= hou_low + “0001”;加一

end if;

end if;

end process shilow;

logo_3 <= hou_low(3)and hou_low(0);

hou_01 <= hou_low;时个位放3

shihigh:process(cy_hou,rst)

begin

if(rst = '0')

then

hou_high <= “0001”;

elsif(cy_hou'event and cy_hou = '1')then检测时进位上升沿

if(hou_high = “0010” and hou_low = “0011”)then若时十位为2，时个位为3

hou_high <= “0000”;

elsif(logo_3 = '1')then

hou_high <= hou_high + “0001”;加一

end if;

end if;

end process shihigh;

bee_clock:process(clk)

begin

if(clk'event and clk = '1')then检测时钟上升沿

if(sec_high = “0101” and sec_low = “1001”

and min_high = “0101” and min_low = “1001”)then

bee <= '1';

else

bee <= '0';

end if;

end if;

end process bee_clock;

hou_1 <= hou_high;时十位放2

end behovior;

library ieee;use ;use ;use ;entity clock1 is port(en

:in std_logic;

clk

:in std_logic;

rst

:in std_logic;sec_1

:out std_logic_vector(3 downto 0);

sec_01 :out std_logic_vector(3 downto 0);min_1

:out std_logic_vector(3 downto 0);

min_01 :out std_logic_vector(3 downto 0);hou_1

:out std_logic_vector(3 downto 0);

hou_01 :out std_logic_vector(3 downto 0);

bee

:out std_logic);end clock1;

architecture behovior of clock1 is signal sec_high:std_logic_vector(3 downto 0);

signal sec_low

:std_logic_vector(3 downto 0);signal min_high:std_logic_vector(3 downto 0);

signal min_low:std_logic_vector(3 downto 0);signal hou_high:std_logic_vector(3 downto 0);

signal hou_low

:std_logic_vector(3 downto 0);

signal cy_min

:std_logic;

signal cy_hou

:std_logic;signal logo_1

:std_logic;

signal logo_2

:std_logic;

signal logo_3

:std_logic;

begin miaolow:process(clk,rst,en)

begin

if(rst = '0')

then

sec_low <= “1000”;

elsif(clk'event and clk = '1' and en = '1')then

if(sec_low = “1001”)then

sec_low <= “0000”;

else

sec_low <= sec_low + “0001”;

end if;

end if;

end process miaolow;

logo_1 <= sec_low(3)and sec_low(0);

sec_01<= sec_low;

miaohigh:process(clk,rst)

begin

if(rst = '0')

then

sec_high <= “0101”;

elsif(clk'event and clk = '1')then

if(logo_1 = '1')then

if(sec_high = “0101”)then

sec_high <= “0000”;

cy_min <= '1';

else

sec_high <= sec_high + “0001”;

cy_min <= '0';

end if;

end if;

end if;

end process miaohigh;

sec_1 <= sec_high;fenlow:process(cy_min,rst,en)

begin

if(rst = '0')

then

min_low <= “1000”;

elsif(cy_min'event and cy_min = '1' and en = '1')then

if(min_low = “1001”)then

min_low <= “0000”;

else

min_low <= min_low + “0001”;

end if;

end if;

end process fenlow;

logo_2 <= min_low(3)and min_low(0);

min_01 <= min_low;

fenhigh:process(cy_min,rst)

begin

if(rst = '0')

then

min_high <= “0101”;

elsif(cy_min'event and cy_min = '1')then

if(logo_2 = '1')then

if(min_high = “0101”)then

min_high <= “0000”;

cy_hou <= '1';

else

min_high <= min_high + “0001”;

cy_hou <= '0';

end if;

end if;

end if;

end process fenhigh;

min_1 <= min_high;shilow:process(cy_hou,rst,en)

begin

if(rst = '0')

then

hou_low <= “1001”;

elsif(cy_hou'event and cy_hou = '1' and en = '1')then

if(hou_low = “1001”)then

hou_low <= “0000”;

elsif(hou_high = “0010” and hou_low = “0011”)then

hou_low <= “0000”;

else

hou_low <= hou_low + “0001”;

end if;

end if;

end process shilow;

logo_3 <= hou_low(3)and hou_low(0);

hou_01 <= hou_low;

shihigh:process(cy_hou,rst)

begin

if(rst = '0')

then

hou_high <= “0001”;

elsif(cy_hou'event and cy_hou = '1')then

if(hou_high = “0010” and hou_low = “0011”)then

hou_high <= “0000”;

elsif(logo_3 = '1')then

hou_high <= hou_high + “0001”;

end if;

end if;

end process shihigh;

bee_clock:process(clk)

begin

if(clk'event and clk = '1')then

if(sec_high = “0101” and sec_low = “1001”

and min_high = “0101” and min_low = “1001”)then

bee <= '1';

else

bee <= '0';

end if;

end if;

end process bee_clock;

hou_1 <= hou_high;

end behovior;

eda简易数字钟设计篇四

eda实现多功能数字钟

实

验 报 告

专业班级：

学生姓名：

学生学号：

目录

一、内容摘要

二、实验要求

三、各底层模块设计

四、总体方案

五、心得体会

一、实验内容

利用 quartusii 软件，结合所学的数字电路的知识设计一个 24 时多功能数 字钟，具有正常分、秒计时，动态显示的功能。分析整个电路的工作原理，分别说明各子模块的设计原理和调试、仿真、编 程的过程。

二、实验任务：

用 fpga 器件和 eda 技术实现多功能数字钟的设计

已知条件：

1、max+plus 软件

2、fpga 实验开发装置

基本功能：

1、以数字形式显示时、分、秒的时间；

2、小时计数器为 24 进制；

3、分、秒计数器为 60 进制。

三、底层模块设计（电路原理图及仿真）

1、小时计数器为24进制 电路原理图

仿真图

封装图

2、分、秒计时器都为60进制 电路原理图

仿真图

封装图

四、总体方案

按照上述实验要求，本次电子数字时钟实验，通过两个模 60 计数器及一个模 24 计数器级联既可以实现计时模块。多功能数字钟的主体部分 电路原理图

仿真图

封装图

五、心得体会

刚刚开始觉得做这个电子实验报告挺难的，因为对软件的不熟悉和对这个实验操作的也不熟悉，对着老师给的资料也做了很长时间，就是仿真的时候有些该注意的没有注意，导致仿真失败，但是后来还是自己慢慢拿的请教同学、老师哪里出了问题，后来才做出来了，把60进制的做出来了，后来的24进制按照老师给的电路原理图也成功了仿真出来，我用了很长时间才编写出来，现在看看，也没有那么难了。同时请教老师，和同学、通过实验掌握一些逻辑组合器件的基本功能和用法。总之，我很感谢这次实验可以给我这样的机会，这个实验给了我很对的收获，我相信这会对我以后的学习很有帮助。